Displays are an important type of medium through which people can receive various kinds of information. The display, as a multimedia display terminal, has a key characteristic, that is, the number of gray levels which the display can present, which is also called a gray-level reproduction ability. A greater number of gray levels which the display can present, i.e., a greater gray-level reproduction ability, cause a higher quality of displayed images, more details of the images, and better visual experiences to human eyes. The number of gray levels depends on the bit width of gray-level data. If the bit width of the gray-level data is N bits, then the display can present gray levels of 0−(2N−1), 2N gray levels in total. In such a case, the display is considered as having an N-bit gray-level reproduction ability. An increase in the gray-level reproduction ability by 1 bit implies a doubled number of gray levels. A Pulse Width Modulation (PWM) based scheme is a main approach to control the gray levels, wherein different gray levels are presented by adjusting a duty cycle of a pulse. Specifically, in an embodiment, a display period T can be determined based on the bit width of the gray-level data, and then the duty cycle can be modulated based on the magnitude of the gray-level data. The modulated duty cycle determines an ON duration of displaying the gray-level data by a display unit during a display period. Let the gray-level data be G, the modulated duty cycle be d, and the ON duration of the display unit be Ton. The following equation holds.
                    {                                                            d                =                                                      G                                          G                      max                                                        =                                      G                                                                  2                        N                                            -                      1                                                                                                                                                                T                  on                                =                                                      d                    ·                    T                                    =                                                            G                                                                        2                          N                                                -                        1                                                              ·                    T                                                                                                          (        1        )            
Take an example where the gray-level data is 8-bit wide. When the gray-level data is varied between 0-255, the corresponding duty cycle d is modulated between 0/255-255/255. In this case, the display can present the gray levels of 0-255, 256 gray levels in total. During a display period, the gray-level data of 0 corresponds to gray level 0, and the gray-level data of 255 corresponds to gray level 255. With this scheme, an increase in the gray-level reproduction ability by 1 bit implies a doubled number of counter clocks for a duty cycle counter in a display period. If a counter clock with the same frequency is used, then the display period is doubled also. For example, 12-bit gray-level data is 4-bit wider than 8-bit gray-level data, and thus the 12-bit gray-level data will render a display period which is 16 times greater than that for the 8-bit gray-level data, given that a counter clock with the same frequency is used. As a result, the display has its refreshing frequency reduced by a factor of 1/16. Such significant reducing in the refreshing frequency causes flicker effects occur on the display, making the displayed image unsuitable to view.
Chinese Patent, published as CN 1326175 on Dec. 12, 2001, patent application no. CN 01123328 filed Apr. 21, 2001, entitled “Modulator Circuit, Image Display with the Modulator Circuit, and Modulation Method”, and whose contents are hereby incorporated by reference in their entirety herein, discloses a modulator circuit with a high resolution PWM to cope with the problems caused by the increased bit width. The modulator circuit is configured to output pulse signals modulated based on values of binary codes. Specifically, the modulator circuit comprises: a selector device configured to divide a binary code from a most significant bit to a least significant bit into several divided binary codes and to select and output the divided binary codes in a preset order; a pulse output device configured to receive the divided binary codes from the selector device and to output pulse signals, with respective pulse widths and levels corresponding to the divided binary codes, in a predetermined period. In this incorporated '328 patent, the modulator circuit divides a binary code, which is intended for modulation of pulse signals, from a most significant bit to a least significant bit into several divided binary codes. The selector divided the predetermined period into sub-frame periods of different lengths corresponding to the respective divided binary codes. Pulse currents in different sub-frame periods are different in value. Take an example where a 14-bit binary code is divided into two divided binary codes, one being 10 most significant bits, and the other being 4 least significant bits, which are indicated as B1 and B2, respectively. The two divided binary codes have corresponding sub-frame periods with lengths of T1 and T2, respectively, and pulse currents of I1 and I2, respectively. T1 and T2, and I1 and I2 exhibit the following relationships: T1=24*T2, and I1=24*I2. Though this method can result in precise control on the gray levels, this method needs to set sub-frame periods of different lengths based on the divided binary codes, leading to more complicated works in software designing. Further, in this method the pulse currents should be adjusted based on the sub-frame periods of different lengths, leading to increased cost of drive hardware.